Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality

Authors:
Matthias Beck;Olivier Barondeau;Martin Kaibel;Frank Poehl;Xijiang Lin;Ron Press
Affiliations:
Infineon Technologies AG, Germany;Infineon Technologies AG, Germany;Infineon Technologies AG, Germany;Infineon Technologies AG, Germany;Mentor Graphics Corporation, Wilsonville, OR;Mentor Graphics Corporation, Wilsonville, OR
Venue:
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Year:
2005

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Abstract

This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed techniques are given.