Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

Authors:
Shianling Wu;Laung-Terng Wang;Xiaoqing Wen;Wen-Ben Jone;Michael S. Hsiao;Fangfang Li;James Chien-Mo Li;Jiun-Lang Huang
Affiliations:
Kyushu Institute of Technology;SynTest Technologies, Inc.;Kyushu Institute of Technology;University of Cincinnati;Virginia Tech;SynTest Technologies, Inc.;National Taiwan University;National Taiwan University
Venue:
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Year:
2012

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Abstract

This article presents a hybrid Automatic Test Pattern Generation (ATPG) technique using the staggered Launch-On-Shift (LOS) scheme followed by the one-hot launch-on-shift scheme for testing delay faults in a scan design containing asynchronous clock domains. Typically, the staggered scheme produces small test sets but needs long ATPG runtime, whereas the one-hot scheme takes short ATPG runtime but yields large test sets. The proposed hybrid technique is intended to reduce test pattern count with acceptable ATPG runtime for multimillion-gate scan designs. In case the scan design contains multiple synchronous clock domains, and each group of synchronous clock domains is treated as a clock group and tested using a launch-aligned or a capture-aligned LOS scheme. By combining these schemes together, we found the pattern counts for two large industrial designs were reduced by approximately 1.6X to 1.8X, while the ATPG runtime was increased by 40% to 50%, when compared to the one-hot clocking scheme alone.