Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
SCOAP: Sandia controllability/observability analysis program
DAC '80 Proceedings of the 17th Design Automation Conference
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Scan-Based Transition Fault Testing " Implementation and Low Cost Test Challenges
ITC '02 Proceedings of the 2002 IEEE International Test Conference
High-Frequency, At-Speed Scan Testing
IEEE Design & Test
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
At-Speed Transition Fault Testing With Low Speed Scan Enable
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Structured delay test using scan transition tests is becoming commonplace. But high coverage andcompact tests can still be elusive in some situations. The authors propose a novel techniquecombining the cost-effectiveness of launch-from-capture test with the coverage/pattern volumeadvantages of launch-from-shift.