COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Skewed-Load Transition Test: Part 1, Calculus
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
SCOAP: Sandia controllability/observability analysis program
DAC '80 Proceedings of the 17th Design Automation Conference
DFT-Focused Chip Testers: What Can They Really Do?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
DFT-Focused Chip Testers - What Can They Do?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Scan-Based Transition Fault Testing " Implementation and Low Cost Test Challenges
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Test set compaction for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Improving Transition Delay Test Using a Hybrid Method
IEEE Design & Test
Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique
Journal of Electronic Testing: Theory and Applications
Conflict driven scan chain configuration for high transition fault coverage and low test power
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel test application scheme for high transition fault coverage and low test cost
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Hazard-based detection conditions for improved transition fault coverage of scan-based tests
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improved launch for higher TDF coverage with fewer test patterns
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An on-chip clock generation scheme for faster-than-at-speed delay testing
Proceedings of the Conference on Design, Automation and Test in Europe
Functional and partially-functional skewed-load tests
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Fixed-state tests for delay faults in scan designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Electronic Testing: Theory and Applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Flip-flop selection for partial enhanced scan to reduce transition test data volume
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Broadside and skewed-load tests under primary input constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design-for-testability for multi-cycle broadside tests by holding of state variables
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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A novel scan-based delay test approach, referred as the hybrid delay scan, is proposed in this paper. The proposed scan-based delay testing method combines advantages of the skewed-load and broad-side approaches. Unlike the skewed-load approach whose design requirement is often too costly to meet due to the fast switching scan enable signal, the hybrid delay scan does not require a strong buffer or buffer tree to drive the fast switching scan enable signal. Hardware overhead added to standard scan designs to implement the hybrid approach is negligible. Since the fast scan enable signal is internally generated, no external pin is required. Transition delay fault coverage achieved by the hybrid approach is equal to or higher than that achieved by the broad-side load for all ISCAS 89 benchmark circuits. On an average, about 4.5% improvement in fault coverage is obtained by the hybrid approach over the broad-side approach.