Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique

Authors:
Swarup Bhunia;Hamid Mahmoodi;Arijit Raychowdhury;Kaushik Roy
Affiliations:
Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, USA 44120;Electrical and Computer Engineering, San Francisco State University, San Francisco, USA;Circuit Reasearch Lab, Intel Corporation, Portland, USA;Electrical and Computer Engineering, Purdue University, West Lafayette, USA
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2008

Citing 12
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Abstract

With increasing defect density and process variations in nanometer technologies, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. This paper presents a novel test technique based on supply gating, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overhead. Experimental results on a set of ISCAS89 benchmarks show an average reduction of 34% in area overhead with an average improvement of 65% in delay overhead and 90% in power overhead during normal mode of operation, compared to the enhanced scan implementation.