A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits

Authors:
Satoshi Ohtake;Hideo Fujiwara;Shunjiro Miwa
Affiliations:
-;-;-
Venue:
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Year:
2002

Citing 0
Cited 2

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique

Journal of Electronic Testing: Theory and Applications
Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τk-Notation

IEICE - Transactions on Information and Systems

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Abstract

This paper shows that path delay fault test generation problem for sequential circuits with balanced structure can be educed to segment delay fault test generation problem for their combinationally transformed circuits. We also propose a test generation method and a partially enhanced scan design method for path delay fault.