The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
Equivalence of robust delay-fault and single stuck-fault test generation
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Sequential logic testing and verification
Sequential logic testing and verification
Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
A New Class of Sequential Circuits with Combinational Test Generation Complexity
IEEE Transactions on Computers
An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits
ATS '98 Proceedings of the 7th Asian Test Symposium
A Complete Characterization of Path Delay Faults through Stuck-at Faults
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Classification of Sequential Circuits Based on "k Notation
ATS '04 Proceedings of the 13th Asian Test Symposium
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Classification of Sequential Circuits Based on τk Notation and Its Applications
IEICE - Transactions on Information and Systems
Easily Testable Sequential Machines with Extra Inputs
IEEE Transactions on Computers
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In this paper, we discuss the relationship between the test generation complexity for path delay faults (PDFs) and that for stuck-at faults (SAFs) in combinational and sequential circuits using the recently introduced τk-notation. On the other hand, we also introduce a class of cyclic sequential circuits that are easily testable, namely two-column distributive state-shiftable finite state machine realizations (2CD-SSFSM). Then, we discuss the relevant conjectures and unsolved problems related to the test generation for sequential circuits with PDFs under different clock schemes and test generation models.