Data structures and network algorithms
Data structures and network algorithms
Digital logic testing and simulation
Digital logic testing and simulation
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Produktionstest synchroner Schaltwerke auf der Basis von Pipelinestrukturen
GI - 18. Jahrestagung II, Vernetzte and komplexe Informatik-Systems
On removing redundancy in sequential circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A design for testability scheme with applications to data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
SIESTA: a multi-facet scan design system
EURO-DAC '92 Proceedings of the conference on European design automation
DAC '93 Proceedings of the 30th international Design Automation Conference
A cost-based approach to partial scan
DAC '93 Proceedings of the 30th international Design Automation Conference
Selective pseudo scan: combinational ATPG with reduced scan in a full custom RISC microprocessor
DAC '93 Proceedings of the 30th international Design Automation Conference
Testability analysis and improvement from VHDL behavioral specifications
EURO-DAC '94 Proceedings of the conference on European design automation
Partial scan selection for user-specified fault coverage
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Test register insertion with minimum hardware cost
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computers
Gate-level test generation for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test point insertion: scan paths through combinational logic
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Reconfigurable scan chains: a novel approach to reduce test application time
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A test synthesis approach to reducing BALLAST DFT overhead
DAC '97 Proceedings of the 34th annual Design Automation Conference
ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
Configuring multiple scan chains for minimum test time
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An IEEE 1149.1 Compliant Test Control Architecture
Journal of Electronic Testing: Theory and Applications
Incremental Testability Analysis for Partial Scan Selection and Design Transformations
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Deterministic BIST with Partial Scan
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
A New Class of Sequential Circuits with Combinational Test Generation Complexity
IEEE Transactions on Computers
ITEM: an iterative improvement test generation procedure for synchronous sequential circuits
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Low-cost sequential ATPG with clock-control DFT
Proceedings of the 39th annual Design Automation Conference
Test generation for acyclic sequential circuits with hold registers
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption
Journal of Electronic Testing: Theory and Applications
IEEE Design & Test
IEEE Design & Test
Optimal Configuring of Multiple Scan Chains
IEEE Transactions on Computers
A layout-based approach for ordering scan chain flip-flops
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Sequential Circuits with combinational Test Generation Complexity
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Sequential Circuit Testing: From DFT to SFT
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
10.1 Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Combinational Test Generation for Various Classes of Acyclic Sequential Circuits
ITC '01 Proceedings of the 2001 IEEE International Test Conference
H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Partial Scan Design Based on Circuit State Information and Functional Analysis
IEEE Transactions on Computers
Reduced Test Application Time Based on Reachability Analysis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Multi-vector tests: a path to perfect error-rate testing
Proceedings of the conference on Design, automation and test in Europe
Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τk-Notation
IEICE - Transactions on Information and Systems
ATPG for heat dissipation minimization during test application
ITC'94 Proceedings of the 1994 international conference on Test
Reduced scan shift: a new testing method for sequential circuits
ITC'94 Proceedings of the 1994 international conference on Test
Configuring flip-flops to BIST registers
ITC'94 Proceedings of the 1994 international conference on Test
Balanced Secure Scan: Partial Scan Approach for Secret Information Protection
Journal of Electronic Testing: Theory and Applications
A New Design-for-Testability Method Based on Thru-Testability
Journal of Electronic Testing: Theory and Applications
Eliminating the Timing Penalty of Scan
Journal of Electronic Testing: Theory and Applications
| Hi-index | 15.00 |
An efficient partial scan technique called Ballast (balanced structure scant test) is presented. Scan path storage elements (SPSEs) are selected such that the remainder of the circuit has certain desirable testability properties. A complete test set is obtained using combinatorial automatic test pattern generation (ATPG). Some SPSEs may need to be provided with a HOLD mode; their number is minimized by ordering the registers in the scan path and formatting the test patterns appropriately. This methodology leads to a low area overhead and allows 100% coverage of irredundant faults.