Test Scheduling and Control for VLSI Built-in Self-Test
IEEE Transactions on Computers
The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
An analytical approach to the partial scan problem
Journal of Electronic Testing: Theory and Applications
Graph partitioning for concurrent test scheduling in VLSI circuit
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Self-Test Scheduling with Bounded Test Execution
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Graph theory: An algorithmic approach (Computer science and applied mathematics)
Graph theory: An algorithmic approach (Computer science and applied mathematics)
A Knowledge-Based System for Designing Testable VLSI Chips
IEEE Design & Test
| Hi-index | 0.00 |
Built-in self-test test registers must segment a circuit such that there exists a feasible test schedule. If a register transfer description is used for selecting the positions of test registers, the space for optimizations is small. In this paper, 1-bit test cells are inserted at gate level, and an initial test schedule is constructed. Based on the information of this schedule, test cells that can be controlled in the same way are assembled to test registers. Finally, a test schedule at RT level is constructed and a minimal set of test control signals is determined. The presented approach can reduce both BIST hardware overhead and test application time. It is applicable to control units and circuits produced by control oriented synthesis where an RT description is not available. Considerable gains can also be obtained if existing RT structures are reconfigured for self-testing in the described way.