Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times

Authors:
Toshinori Hosokawa;Masayoshi Yoshimura;Mitsuyasu Ohta
Affiliations:
Corporate Semiconductor Development Division, Matsushita Electric Industrial Co., Ltd. / Design Technology Development Department, Semiconductor Technology Academic Research Center, 6-16-10, Shimb ...;Corporate Semiconductor Development Division, Matsushita Electric Industrial Co., Ltd., 1, Kotari-yakemachi, Nagaokakyo, Kyoto 617-8520, Japan;Corporate Semiconductor Development Division, Matsushita Electric Industrial Co., Ltd., 1, Kotari-yakemachi, Nagaokakyo, Kyoto 617-8520, Japan
Venue:
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Year:
2001

Citing 7
Cited 0

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Abstract

As an LSI is on the two-dimensional plane, the number of external pins of an LSI does not equally increase to the number of gates. Therefore, the number of flip-flops on a scan path is relatively increasing. As the results, the test application time becomes longer. In this paper, three new DFT strategies are proposed to reduce the test application time. Experimental results showed the DFT strategies reduced the test application times by 46 to 82% compared with a conventional full scan design method.