The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Introduction to algorithms
DFT Expert: Designing Testable VLSI Circuits
IEEE Design & Test
Selectable Length Partial Scan: A Method to Reduce Vector Length
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Optimal Sequencing of Scan Registers
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
SIESTA: a multi-facet scan design system
EURO-DAC '92 Proceedings of the conference on European design automation
Configuring multiple scan chains for minimum test time
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An IEEE 1149.1 Compliant Test Control Architecture
Journal of Electronic Testing: Theory and Applications
Deterministic BIST with Multiple Scan Chains
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A layout-based approach for ordering scan chain flip-flops
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Proceedings of the 40th annual Design Automation Conference
Benefits of a SoC-Specific Test Methodology
IEEE Design & Test
Testable design of non-scan sequential circuits using extra logic
ATS '95 Proceedings of the 4th Asian Test Symposium
Partial Scan Design Based on Circuit State Information and Functional Analysis
IEEE Transactions on Computers
Two efficient methods to reduce power and testing time
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Reducing test application time, test data volume and test power through Virtual Chain Partition
Integration, the VLSI Journal
| Hi-index | 14.99 |
To reduce the high test time for serial scan designs, the use of multiple scan chains has been proposed. In this paper, the authors consider the problem of optimally constructing the multiple scan chains to minimize the overall test time. Rather than follow the traditional practice of using equal length chains, the authors allow the chains to be of different lengths and show that this cap lead to lower test times. The main idea in this approach is to place those scan elements that are more frequently accessed in shorter scan chains as this tends to reduce the overall test time. Given a design with N scan elements and given that if scan chains need to be used for applying tests, the authors present an algorithm of complexity O(kN/sup 2/) for constructing the specified number of chains such that the overall test application time is minimized. By analyzing a range of different circuit topologies, the authors demonstrate test time reductions as large as 40% over equal length chains.