Optimal Configuring of Multiple Scan Chains
IEEE Transactions on Computers
Selectable Length Partial Scan: A Method to Reduce Vector Length
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Reconfiguration techniques for a single scan chain
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Changing the Scan Enable during Shift
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Two efficient methods to reduce power and testing time
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Reducing scan shifts using configurations of compatible and folding scan trees
Journal of Electronic Testing: Theory and Applications
| Hi-index | 4.10 |
Two factors primarily drive the soaringcost of semiconductor test: thenumber of test patterns applied toeach chip and the time it takes to runeach pattern. Typical semiconductortesting for each chip involves a set of1,000 to 5,000 test patterns. These testsare applied through scan chains thatoperate at about 25 MHz. Depending onthe size of the scan chains on the chip, aset of test patterns can take a few secondsto execute per chip.It's easy to see that even a smalldecrease in either the number of patternsor the time to execute them can quicklyadd up to big savings across millions offabricated chips. This potential savingsforms the basis for dynamic scan, a newapproach to the well-established scan testmethodology.The authors' initial studies indicate thatdynamic scan could easily reduce the timespent applying test patterns by 40 percent.A more theoretical analysis shows apotential savings of as much as 80 percent.