A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Proceedings of the 40th annual Design Automation Conference
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On Test Data Volume Reduction for Multiple Scan Chain Designs
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient BIST TPG design and test set compaction via input reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, a new method for reducing scan shifts is presented. Scan design is one of the most popular designs for test method for sequential circuits. However, for circuits with many flip-flops, it requires a long test application time and high test-data volume. Our new scan method utilizes two configurations of scan chains, a folding scan tree and a fully compatible scan tree to alleviate these problems. It is observed that uncompacted test patterns typically contain a large fraction of don't care values. This property is exploited in the fully compatible scan tree to reduce scan shifts without degrading fault coverage. Then, a folding scan tree is configured to further reduce the length of scan chain and scan shifts. Experimental results on benchmark circuits show that this scan method can significantly reduce scan shifts.