Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Proceedings of the 40th annual Design Automation Conference
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
On Test Data Volume Reduction for Multiple Scan Chain Designs
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
IEEE Transactions on Computers
An Efficient Scan Tree Design for Test Time Reduction
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
Multiple Scan Tree Design with Test Vector Modification
ATS '04 Proceedings of the 13th Asian Test Symposium
Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Reducing scan shifts using configurations of compatible and folding scan trees
Journal of Electronic Testing: Theory and Applications
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction
IEEE Transactions on Computers
Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis
ATS '07 Proceedings of the 16th Asian Test Symposium
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
Low-power scan testing for test data compression using a routing-driven scan architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Broadcasting test patterns to multiple circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Efficient Scan Tree Design for Compact Test Pattern Set
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test set compaction for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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A synthesis methodology for multiple scan trees that considers output pin limitation, scan chain routing length, test application time, and test data compression rate simultaneously is proposed in this paper. Multiple scan trees, also known as a scan forest, greatly reduce test data volume and test application time in system-on-chip testing. However, previous research on scan tree synthesis rarely considered issues such as, routing length and output port limitation, and hence created scan trees with a large number of scan output ports and excessively long routing paths. The proposed algorithm provides a mechanism that effectively reduces test time and test data volume, and routing length under output port constraint. As a result, very few or no output compressors are required, which significantly reduces the hardware overhead.