IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A new scan architecture called reconfigured scan forest is proposed for cost-effective scan testing. Multiple scan flip-flops can be grouped based on structural analysis that avoids new untestable faults due to new reconvergen t fanouts. The proposed new scan architecture makes all scan flip-flop groups have similar size because of flexibility of the scan flip-flop grouping scheme, where many scan flip-flops become internal scan flip-flops. The size of the exclusive-or trees can be reduced greatly compared with the original scan forest. Therefore, area overhead and routing complexity are reduced greatly. It is shown that test application cost and test pow er with the proposed scan forest architecture can be reduced t~ even less than 1% of the con venntional full scan design with a single scan chain.