An Efficient Scan Tree Design for Test Time Reduction

Authors:
Y. Bonhomme;T. Yoneda;H. Fujiwara;P. Girard
Affiliations:
Nara Institute of Science and Technology;Nara Institute of Science and Technology;Nara Institute of Science and Technology;Université Montpellier II/CNRS, France
Venue:
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
Year:
2004

Citing 0
Cited 3

Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction

IEEE Transactions on Computers
Reducing test application time, test data volume and test power through Virtual Chain Partition

Integration, the VLSI Journal
Multiple scan trees synthesis for test time/data and routing length reduction under output constraint

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

During the past years, due to the decrease of the minimum feature size in CMOS technology, the on-chip clock frequencies have increased dramatically ranging into the GHz domain.This increase has also pushed the need for higher data-transfer rates between ...