Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis

Authors:
Sying-Jyan Wang;Xin-Long Li;Katherine Shu-Min Li
Affiliations:
National Chung Hsing University, Taiwan;National Chung Hsing University, Taiwan;National Sun Yat-Sen University, Taiwan
Venue:
ATS '07 Proceedings of the 16th Asian Test Symposium
Year:
2007

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Multiple scan trees synthesis for test time/data and routing length reduction under output constraint

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Abstract

In this paper, we propose a layout-aware scan tree synthesis methodology. Scan tree can greatly reduce test data volume, which is very desirable in SOC testing. However, previous researches on scan tree synthesis have not considered routing issues in physical design, which may create a tree with excessively long routing path. In this paper we present a multi-layer multi-level scan tree synthesis method, in which both data compression and routing length are taken into account. Experimental results show that the proposed test method achieves high compression rate with limited routing overhead.