On test data compression and n-detection test sets
Proceedings of the 40th annual Design Automation Conference
Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes
Journal of Electronic Testing: Theory and Applications
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
On Compacting Test Response Data Containing Unknown Values
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Adjustable Width Linear Combinational Scan Vector Decompression
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Test data compression technique using selective don't-care identification
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Evolutionary Optimization in Code-Based Test Compression
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Journal of Electronic Testing: Theory and Applications
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Reducing scan shifts using configurations of compatible and folding scan trees
Journal of Electronic Testing: Theory and Applications
On test data compression using selective don't-care identification
Journal of Computer Science and Technology
Survey of Test Vector Compression Techniques
IEEE Design & Test
Scan-BIST based on cluster analysis and the encoding of repeating sequences
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test data compression scheme based on variable-to-fixed-plus-variable-length coding
Journal of Systems Architecture: the EUROMICRO Journal
Scan-chain partition for high test-data compressibility and low shift power under routing constraint
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test data compression using efficient bitmask and dictionary selection methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Capture-power-aware test data compression using selective encoding
Integration, the VLSI Journal
COMPAS – compressed test pattern sequencer for scan based circuits
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
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We consider issues related to the reduction of scan test data in designs with multiple scan chains. We propose metric that can be used to evaluate the effectiveness of procedures for reducing the scan data volume. The metric compares the achieved compression to the compression which is intrinsic to the use of multiple scan chains. We also propose a procedure for modifying a given test set so as to achieve reductions in test data volume assuming combinational decompressor circuit.