Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Seed encoding with LFSRs and cellular automata
Proceedings of the 40th annual Design Automation Conference
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Packet-Based Input Test Data Compression Techniques
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Don't-Care Identification on Specific Bits of Test Patterns
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
How Effective are Compression Codes for Reducing Test Data Volume?
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
On Test Data Volume Reduction for Multiple Scan Chain Designs
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
IEEE Transactions on Computers
Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design of Routing-Constrained Low Power Scan Chains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction
IEEE Transactions on Computers
Optimal Selective Huffman Coding for Test-Data Compression
IEEE Transactions on Computers
Layout-aware scan chain reorder for launch-off-shift transition test coverage
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multilevel-Huffman test-data compression for IP cores with multiple scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Broadcasting test patterns to multiple circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test set compaction algorithms for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test data compression and decompression based on internal scan chains and Golomb coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variable-length input Huffman coding for system-on-a-chip test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Relationship Between Entropy and Test Data Compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test Data Compression Using Selective Sparse Storage
Journal of Electronic Testing: Theory and Applications
Test data compression using interval broadcast scan for embedded cores
Microelectronics Journal
Virtual scan chains reordering using a RAM-based module for high test compression
Microelectronics Journal
Scan power reduction for linear test compression schemes through seed selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Journal on Emerging Technologies in Computing Systems (JETC)
| Hi-index | 0.03 |
The degree of achievable test-data compression depends on not only the compression scheme but also the structure of the applied test data. Therefore, it is possible to improve the compression rate of a given test set by carefully organizing the way that test data are present in the scan structure. The relationship between signal probability and test-data entropy is explored in this paper, and the results show that the theoretical maximum compression can be increased through a partition of scan flip-flops such that the test data present in each partition have a skewed signal distribution. In essence, this approach simply puts similar scan flip-flops in an adjacent part of a scan chain, which also helps to reduce shift power in the scan test process. Furthermore, it is shown that the intrapartition scan-chain order has little impact on the compressibility of a test set; thus, it is easy to achieve higher test compression with low routing overhead. Experimental results show that the proposed partition method can raise the compression rates of various compression schemes by more than 17%, and the average reduction in shift power is about 50%. In contrast, the increase in routing length is limited.