Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
How Effective are Compression Codes for Reducing Test Data Volume?
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
A hamming distance based VLIW/EPIC code compression technique
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DATA COMPRESSION FOR MULTIPLE SCAN CHAINS USING DICTIONARIES WITH CORRECTIONS
ITC '04 Proceedings of the International Test Conference on International Test Conference
Survey of Test Vector Compression Techniques
IEEE Design & Test
Optimal Selective Huffman Coding for Test-Data Compression
IEEE Transactions on Computers
Scan-chain partition for high test-data compressibility and low shift power under routing constraint
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Data Compression Using Multi-dimensional Pattern Run-length Codes
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression using selective encoding of scan slices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression using four-coded and sparse storage for testing embedded core
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A unified approach to reduce SOC test data volume, scan power and testing time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variable-length input Huffman coding for system-on-a-chip test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bitmask-Based Code Compression for Embedded Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Virtual scan chains reordering using a RAM-based module for high test compression
Microelectronics Journal
Hi-index | 0.00 |
For today's very large scale integrated circuits, test data volume is recognized as a major contributor to the cost of manufacturing testing. Test data compression addresses this problem by reducing the test data volume without affecting the overall system performance. This paper proposes a new test data compression technique using selective sparse storage. Test sets are partitioned into four kinds of blocks of uniform length, all-0 blocks, all-1 blocks, sparse blocks and characterless blocks. Blocks are encoded appropriately based on the occurrence of them. They are encoded into 0, 10, 110 + number of the sparse bits + locations of all the sparse bits, and 111 + the block itself, respectively. Two algorithms are proposed for how to select the sparse blocks from test sets. A theoretical analysis for our selective sparse storage shows the new compression technique outperforms the conventional test data compression approaches. Experimental results illustrate the flexibility and efficiency of the new method, which is consistent with the theoretical analysis.