Deterministic Built-in Pattern Generation for Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
IEEE Transactions on Computers
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient test-data compression for IP cores using multilevel Huffman coding
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test set compaction algorithms for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A unified approach to reduce SOC test data volume, scan power and testing time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variable-length input Huffman coding for system-on-a-chip test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
State skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores
Proceedings of the conference on Design, automation and test in Europe
The use of genetic programming for adaptive text compression
International Journal of Information and Coding Theory
Scan-chain partition for high test-data compressibility and low shift power under routing constraint
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Data Compression Using Multi-dimensional Pattern Run-length Codes
Journal of Electronic Testing: Theory and Applications
A novel x-ploiting strategy for improving performance of test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Electronic Testing: Theory and Applications
Test data compression using efficient bitmask and dictionary selection methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of test data compression techniques emphasizing statistical coding schemes
Proceedings of the International Conference & Workshop on Emerging Trends in Technology
Test Data Compression Using Selective Sparse Storage
Journal of Electronic Testing: Theory and Applications
Test data compression using interval broadcast scan for embedded cores
Microelectronics Journal
Achieving low capture and shift power in linear decompressor-based test compression environment
Microelectronics Journal
Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs
Proceedings of the International Conference on Computer-Aided Design
A fast algorithm for Huffman decoding based on a recursion Huffman tree
Journal of Systems and Software
A modified scheme for simultaneous reduction of test data volume and testing power
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Virtual scan chains reordering using a RAM-based module for high test compression
Microelectronics Journal
Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding
Journal of Electronic Testing: Theory and Applications
| Hi-index | 14.98 |
Selective Huffman coding has been recently proposed for efficient test-data compression with low hardware overhead. In this paper we show that the already proposed encoding scheme is not optimal and we present a new one, proving that it is optimal. Moreover, we compare the two encodings theoretically and we derive a set of conditions which show that, in practical cases, the proposed encoding offers always better compression. In terms of hardware overhead, the new scheme is at least as low-demanding as the old one. The increased compression efficiency, the resulting test-time savings, and the low hardware overhead of the proposed method are also verified experimentally.