Seed encoding with LFSRs and cellular automata
Proceedings of the 40th annual Design Automation Conference
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Optimal Selective Huffman Coding for Test-Data Compression
IEEE Transactions on Computers
Proceedings of the conference on Design, automation and test in Europe
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Broadcasting test patterns to multiple circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-Power Test Data Application in EDT Environment Through Decompressor Freeze
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Growing test data volume and excessive power dissipation are two major issues in testing of very large scale integrated (VLSI) circuits. Most previous low power techniques cannot work well with test-data compression schemes. Even if some low power methods can be applied in a test compression environment, they cannot reduce shift power and capture power simultaneously. This paper presents a new low shift-in power scan testing scheme in linear decompressor-based test compression environment. By dividing the test cubes into two kinds of blocks: non-transitional (low toggles) and transitional (with toggles) and feeding scan chains with these blocks through a novel DFT architecture, this approach can effectively reduce the quantity of transitions while scanning-in a test pattern. A low capture and shift-out power X-filling method compatible with the scan testing scheme is also proposed. The X-filling method assigns an interdependent X-bits set at each run and achieves significant power reduction. Interestingly, in the comprehensive strategy, capture power reduction agrees with shift-out power reduction to a certain extent. Experimental results on the larger ISCAS'89 and ITC'99 benchmark circuits show that the holistic strategy can reduce test power in shift cycles and capture cycles significantly under the constraint of certain compression ratio.