ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Reducing Power Dissipation during Test Using Scan Chain Disable
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Controlling Peak Power During Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
On test generation for transition faults with minimized peak power dissipation
Proceedings of the 41st annual Design Automation Conference
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
A Scan Chain Adjustment Technology for Test Power Reduction
ATS '06 Proceedings of the 15th Asian Test Symposium
Low Shift and Capture Power Scan Tests
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Low-power scan design using first-level supply gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On capture power-aware test data compression for scan-based testing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
On systematic illegal state identification for pseudo-functional testing
Proceedings of the 46th Annual Design Automation Conference
A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Defect aware X-filling for low-power scan testing
Proceedings of the Conference on Design, Automation and Test in Europe
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects
Proceedings of the Conference on Design, Automation and Test in Europe
A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
X-filling for simultaneous shift- and capture-power reduction in at-speed scan-based testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A physical-location-aware fault redistribution for maximum IR-drop reduction
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Compression-aware capture power reduction for at-speed testing
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Capture-power-aware test data compression using selective encoding
Integration, the VLSI Journal
Achieving low capture and shift power in linear decompressor-based test compression environment
Microelectronics Journal
Pseudo-functional testing for small delay defects considering power supply noise effects
Proceedings of the International Conference on Computer-Aided Design
A physical-location-aware X-bit redistribution for maximum IR-drop reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In scan-based tests, power consumptions in both shift and capture phases may be significantly higher than that in normal mode, which threatens circuits' reliability during manufacturing test. In this paper, by analyzing the impact of X-bits on circuit switching activities, we present an X-filling technique that can decrease both shift- and capture-power to guarantees the reliability of scan tests, called iFill. Moreover, different from prior work on X-filling for shift-power reduction which can only reduce shift-in power, iFill is able to decrease power consumptions during both shift-in and shift-out. Experimental results on ISCAS'89 benchmark circuits show the effectiveness of the proposed technique.