Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Comparing Functional and Structural Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Proceedings of the conference on Design, automation and test in Europe - Volume 2
On Generating Pseudo-Functional Delay Fault Tests for Scan Designs
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
A Novel Transition Fault ATPG That Reduces Yield Loss
IEEE Design & Test
Critical-path-aware X-filling for effective IR-drop reduction in at-speed scan testing
Proceedings of the 44th annual Design Automation Conference
Modeling Power Supply Noise in Delay Testing
IEEE Design & Test
Scan-Based Tests with Low Switching Activity
IEEE Design & Test
Proceedings of the conference on Design, automation and test in Europe
Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
On systematic illegal state identification for pseudo-functional testing
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pseudo-functional testing for small delay defects considering power supply noise effects
Proceedings of the International Conference on Computer-Aided Design
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs
Proceedings of the International Conference on Computer-Aided Design
A scalable quantitative measure of IR-drop effects for scan pattern generation
Proceedings of the International Conference on Computer-Aided Design
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When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of the circuits. In this paper, we propose novel layout-aware pseudo-functional testing techniques to tackle the above problem. Firstly, by taking the circuit layout information into account, functional constraints related to delay faults on critical paths are extracted. Then, we generate functionally-reachable test cubes for every true critical path in the circuit. Finally, we fill the don't-care bits in the test cubes to maximize power supply noises on critical paths under the consideration of functional constraints. The effectiveness of the proposed methodology is verified with large ISCAS'89 benchmark circuits.