Built-in self-test for signal integrity
Proceedings of the 38th annual Design Automation Conference
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
Journal of Electronic Testing: Theory and Applications
3D direct vertical interconnect microprocessors test vehicle
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Testing Interconnects for Noise and Skew in Gigahertz SoCs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Layout-aware, IR-drop tolerant transition fault pattern generation
Proceedings of the conference on Design, automation and test in Europe
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Novel physical unclonable function with process and environmental variations
Proceedings of the Conference on Design, Automation and Test in Europe
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects
Proceedings of the Conference on Design, Automation and Test in Europe
Modeling and estimation of power supply noise using linear programming
Proceedings of the International Conference on Computer-Aided Design
Journal of Electronic Testing: Theory and Applications
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To achieve high performance and high integration density, the transistor dimensions are aggressively scaled down while lower power dissipation is achieved by scaling down the supply voltage. However, power distribution has become a challenging issue due to the severe switching noise on the power distribution network. Estimation of the worst case switching noise is essential to ensure the proper functionality of the VLSI circuits.In this paper, we propose a probabilistic approach to determine the worst case switching noise on power supply lines. The proposed algorithm traces the worst case input patterns which will induce the steepest maximum switching current spike and therefore the maximum switching noise. The worst case input patterns are used in the HSPICE simulation to extract the exact switching current waveforms. The estimated maximum switching current spike matches well with the peak current obtained from the HSPICE simulation. The worst case switching noise due to the lumped inductance (including the packaging inductance) and the lumped resistance on the power supply grid is also extracted from the HSPICE simulation. The magnitude of the worst case switching noise for the benchmark circuits implemented with 0.25 micron technology can be as high as 35\% of the Vdd. The switching noise can be suppressed effectively with properly placed decoupling capacitors.