CMOS current steering logic for low-voltage mixed-signal integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Three-Dimensional Cache Design Exploration Using 3DCacti
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Implementing Caches in a 3D Technology for High Performance Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Thermal Trends in Emerging Technologies
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Die Stacking (3D) Microarchitecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
A modular 3d processor for flexible product design and technology migration
Proceedings of the 5th conference on Computing frontiers
Design space exploration for 3-D cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Invited paper: Thermal modeling and analysis of 3D multi-processor chips
Integration, the VLSI Journal
2.5-Dimensional VLSI system integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The current trends in high performance integrated circuits are towards faster and more powerful circuits in the giga-hertz range and even further. As the more complex Integrated Circuits (IC) such as microprocessors have been entering the giga-hertz operating frequency range, various speed related roadblocks have become increasingly difficult to overcome. The migration to smaller devices has raised serious challenges. The major impediment to fulfill Moore's Law effectively in the years to come is increasingly becoming the interconnect. ICs are using a greater fraction of their clock cycles charging interconnect wires. IC interconnect related speed degradation has stimulated much research effort in the area of low dielectric constant materials. A relatively novel approach, wafer scale 3-dimensional (3D) integration attempts to by-pass the large wire parasitics by shortening wires. This paper is going to elaborate on a 3D microprocessor test vehicle. We intend to demonstrate the speed advantages, which may be derived from 3D integration, through a combination of fabrication, testing and simulation.