Analysis of High-Performance Flip-Flops for Submicron Mixed-Signal Applications
Analog Integrated Circuits and Signal Processing
An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
3D direct vertical interconnect microprocessors test vehicle
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Design of ultrahigh-speed low-voltage CMOS CML buffers and latches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A quiet logic family-complementary metal-oxide-semiconductor (CMOS) current steering logic (CSL)-has been developed for use in low-voltage mixed-signal integrated circuits. Compared to a CMOS static logic gate with its output range of /spl Delta/V/sub logic//spl ap/V/sub dd/, a CSL gate swings only /spl Delta/V/sub logic//spl ap/V/sub T/+0.25 V because the constant current supplied by the PMOS load device is steered to ground through either an NMOS diode-connected device or switching network. Owing to the constant current, digital switching noise is 100/spl times/ smaller than in static logic. Another useful feature which can be used to calibrate CSL speed against process, temperature, and voltage variations is propagation delay that is approximately constant versus supply voltage and linear with bias current. Several CSL circuits have been fabricated using 0.8 and 1.2 /spl mu/m high-V/sub T/ n-well CMOS processes. Two self-loaded 39-stage ring oscillators fabricated using the 1.2 /spl mu/m process (1.2 V power supply) exhibited power-delay products of 12 and 70 fJ with average propagation delays of 0.4 and 0.7 ns, respectively. High-V/sub T/ and low-V/sub T/ CSL ALU's were operational at V/sub dd//spl ap/=0.70 V and V/sub dd//spl ap/0.40 V, respectively.