Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
CMOS current steering logic for low-voltage mixed-signal integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Logic-Level fast current simulation for digital CMOS circuits
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Optimization of master-slave flip-flops for high-performance applications
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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This paper presents a detailed analysis of high-performanceedge-triggered memory elements for deep submicron mixed-signalapplications. The variations of the main parameters (power, delay,peak of supply current) with supply voltage, as well as timingrestrictions have been studied. Especial emphasis has been given toswitching-noise generation, an aspect of important concern inmixed-signal applications. We have analyzed the sources ofswitching noise, noticing that, the less noisy flip-flops are thosebased on differential structures.