Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
CMOS current steering logic for low-voltage mixed-signal integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
A 10Gbps analog adaptive equalizer and pulse shaping circuit for backplane interface
CSECS'06 Proceedings of the 5th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2008 custom integrated circuits conference (CICC 2008)
A 3.4Gbps transmitter for multi-serial data communication using pre-emphasis method
CISST'10 Proceedings of the 4th WSEAS international conference on Circuits, systems, signal and telecommunications
A 32Gbps low propagation delay 4x4 switch IC for feedback-based system in 0.13μm CMOS technology
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Output resistance scaling model for deep-submicron cmos buffers for timing performance optimisation
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A simple MOSFET parasitic capacitance model and its application to repeater insertion technique
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
An on-chip global broadcast network design with equalized transmission lines in the 1024-core era
Proceedings of the International Workshop on System Level Interconnect Prediction
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A comprehensive study of ultrahigh-speed currentmode logic (CML) buffers along with the design of novel regenerative CML latches will be illustrated. First, a new design procedure to systematically design a chain of tapered CML buffers is proposed. Next, two new high-speed regenerative latch circuits capable of operating at ultrahigh-speed datarates will be introduced. Experimental results show a higher performance for the new latch architectures compared to the conventional CML latch circuit at ultrahigh-frequencies. It is also shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications.