A 10Gbps analog adaptive equalizer and pulse shaping circuit for backplane interface

Authors:
Kwisung Yoo;Gunhee Han;Sungmin Park
Affiliations:
Department of Electrical and Electronic Engineering, Yonsei University, Seodaemun-gu, Seoul, Republic of Korea;Department of Electrical and Electronic Engineering, Yonsei University, Seodaemun-gu, Seoul, Republic of Korea;Department of Electrical and Electronic Engineering, Yonsei University, Seodaemun-gu, Seoul, Republic of Korea
Venue:
CSECS'06 Proceedings of the 5th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing
Year:
2006

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Abstract

The speed of serial interface through a backplane channel suffers severe ISI (Inter Symbol Interference) caused by the limited bandwidth of the channel. In order to overcome the bandwidth limit, a pulse shaping circuit or an adaptive equalizer is used. This paper presents the comparison between two approaches. Prototype chip is designed for 10Gbps serial data communication through a 34-inch transmission line with a 0.18-??? CMOS process. The simulation and layout results show that the adaptive equalization has superior performance in power consumption, silicon area and the jitter performance.