Design of ultrahigh-speed low-voltage CMOS CML buffers and latches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Repeater insertion is one of the most effective techniques to reduce the propagation delay related to long interconnects. However, its application to deep submicron technologies leads to sub-optimal results if the traditional sizing rules are followed. In the paper the Authors show the behaviour of deep-sub micron devices may differ significantly from the conventional one due to transistor parasitic capacitance. As a consequence, well-exploited assumption as linear relationship between channel width and output conductance of the CMOS gate start to fails, as well as it does optimisation techniques based upon them. A developed formula for buffer sizing is proposed based on a simplified model allowing MOS parasitic to be taken into account. Up to 50% area and leakage power saving can be obtained.