A low power 13-Gb/s 2^7-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Design of ultrahigh-speed low-voltage CMOS CML buffers and latches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, a low propagation delay, low power, and area-efficient 4x4 load-balanced switch circuit for feedback-based system is presented. In this periodic and deterministic switch, only two DFFs are used to implement a pattern generator which is a O(N3) hardware complexity in traditional matching algorithm based NxN switch. For packet reordering, a feedback path is established in series of symmetric patterns. As comparing with commercial switch systems, we implement a 4x4 switch IC directly in high speed domain without the use of SERDES interfaces to achieve low propagation delay and high scalability. In CML output buffer, PMOS active load and active back-end termination are introduced. A stacked current source and symmetric topology in CML-DFF are adopted. From our results, this work efficiently deducted 28ns propagation delay, 80% area and 80% power introduced by the SERDES interface. The throughput rate is up to 32Gbps (8Gbps/Ch).