An on-chip global broadcast network design with equalized transmission lines in the 1024-core era

Authors:
Guang Sun;Shih-Hung Weng;Chung-Kuan Cheng;Bill Lin;Lieguang Zeng
Affiliations:
Tsinghua University and University of California, San Diego;University of California, San Diego;University of California, San Diego;University of California, San Diego;Tsinghua University
Venue:
Proceedings of the International Workshop on System Level Interconnect Prediction
Year:
2012

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Abstract

Based on current trends in multicore scaling, chips with 1024 cores may be available within the next decade. For such number of cores, cache coherence becomes a critical challenge because of the broadcasting operation. For the conventional electrical mesh interconnect network, broadcasting common data to all the cores is difficult to perform efficiently. In this paper, we developed a high-throughput, low-latency and power-efficient equalized dense transmission line (T-line) structure tailored for efficient global broadcasting. Moreover, we propose a hierarchical architecture and an efficient physical structure for 1024-core communication. Evaluation results show high performance of our solution.