A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Passive Synthesis of Compact Frequency-Dependent Interconnect Models via Quadrature Spectral Rules
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Prediction of high-performance on-chip global interconnection
Proceedings of the 11th international workshop on System level interconnect prediction
On the impact of on-chip inductance on signal nets under the influence of power grid noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An on-chip global broadcast network design with equalized transmission lines in the 1024-core era
Proceedings of the International Workshop on System Level Interconnect Prediction
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Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix and its inverse, 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods . Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach. It then extends the extraction algorithm to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis.