Generating sparse partial inductance matrices with guaranteed stability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Figures of merit to characterize the importance of on-chip inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Dealing with inductance in high-speed chip design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
IC analyses including extracted inductance models
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On-chip inductance issues in multiconductor systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Optimum positioning of interleaved repeaters In bidirectional buses
Proceedings of the 40th annual Design Automation Conference
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Quick On-Chip Self- and Mutual-Inductance Screen
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Inductance calculations in a complex integrated circuit environment
IBM Journal of Research and Development
On-chip inductance cons and pros
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-chip induction modeling: basics and advanced methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Managing on-chip inductive effects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An analytical delay model for RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equivalent Elmore delay for RLC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs
Microelectronics Journal
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It has been well recognized that the impact of on-chip inductance on some critical nets, such as clock nets, is significant and cannot be ignored in delay modeling for these nets. However, the impact of on-chip inductance on signal nets in general is still not well understood. We present results of analyzing inductive effects on signal nets for ultradeep submicron technologies under the influence of power grid noise. The analysis is based on an Al-based 0.18-µm CMOS process and a Cu-based 0.13-µm CMOS process. The impact of on-chip inductance is shown to be insignificant if we assume a perfect power supply network around the interconnect routes. Otherwise, the impact of on-chip inductance can be significant. Furthermore, the results presented in this paper illustrate the impact of on-chip inductance one would expect from transitioning from an Al-based interconnect technology to a Cu-based interconnect technology. A heuristic method is proposed in the paper to account for the inductive coupling due to power grid noise in signal delay modeling and simulations.