Reducing signal timing variations in inter-core busses
Integration, the VLSI Journal
On the impact of on-chip inductance on signal nets under the influence of power grid noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Modeling magnetic interactions for on-chip interconnect has become an issue of great interest for integrated circuit design in recent years. This paper describes the basic concepts of magnetic interaction, loop and partial inductance, along with some of the high frequency effects such as skin and proximity effect. We also discuss and contrast options for stable and accurate window-based extraction of large-scale magnetic coupling. We analyze the required window sizes to consider the possibilities for pattern-matching style solutions, and propose three schemes for determining coupling values and window sizing for extraction via on-the-fly field solution.