High-speed signal propagation on lossy transmission lines
IBM Journal of Research and Development
Modeling and characterization of long on-chip interconnections for high-performance microprocessors
IBM Journal of Research and Development
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
High-Speed Digital Circuits
Power dissipated by CMOS gates driving lossless transmission lines
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Interconnect coupling noise in CMOS VLSI circuits
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Getting to the bottom of deep submicron II: a global wiring paradigm
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Equivalent Elmore delay for RLC trees
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On-chip inductance issues in multiconductor systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Theoretical limits for signal reflections due to inductance for on-chip interconnections
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Repeater insertion in tree structured inductive interconnect
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Noise-aware power optimization for on-chip interconnect
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
On the impact of on-chip inductance on signal nets under the influence of power grid noise
Proceedings of the conference on Design, automation and test in Europe
Min/max on-chip inductance models and delay metrics
Proceedings of the 38th annual Design Automation Conference
Exploiting the on-chip inductance in high-speed clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Full-chip, three-dimensional, shapes-based RLC extraction
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Formulae and applications of interconnect estimation considering shield insertion and net ordering
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Practical considerations in RLCK crosstalk analysis for digital integrated circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Impact of On-Chip Inductance When Transitioning from Al to Cu Based Technology
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Quick On-Chip Self- and Mutual-Inductance Screen
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Expanding the frequency range of AWE via time shifting
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A new RLC buffer insertion algorithm
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Analytical timing model for inductance-dominant interconnect based on traveling wave propagation
Microelectronics Journal
Analysis of high-performance clock networks with RLC and transmission line effects
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
DSM interconnects: importance of inductance effects and corresponding range of length
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the impact of on-chip inductance on signal nets under the influence of power grid noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Differential current-sensing for on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A closed form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer technologies. Two figures of merit are presented that are useful for determining if a section of interconnect should be modeled as either an RLC or an RC impedance. The damping factor of a lumped RLC circuit is shown to be a useful figure of merit. The second useful figure of merit considered in this paper is the ratio of the rise time of the input signal at the driver of an interconnect line to the time of flight of the signals across the line. AS/X circuit simulations of an RLC transmission line and a five section RC II circuit based on a 0.25 µm IBM CMOS technology are used to quantify and determine the relative accuracy of an RC model. One primary result of this study is evidence demonstrating that a range for the length of the interconnect exists for which inductance effects are prominent. Furthermore, it is shown that under certain conditions, inductance effects are negligible despite the length of the section of interconnect.