Modeling and characterization of long on-chip interconnections for high-performance microprocessors
IBM Journal of Research and Development
Delay and Power Expressions for a CMOS Inverter Drivinga Resistive-Capacitive Load
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
Ramp Input Response of RC Tree Networks
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
Figures of merit to characterize the importance of on-chip inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The dynamic and short-circuit power consumption of a CMOS gate driving an LC transmission line as a limiting case of an RLC transmission line is investigated in this paper. Closed form solutions for the output voltage and short-circuit power of a CMOS gate driving an LC transmission line are presented. These solutions agree with AS/X simulations within 11% error for a wide range of transistor widths and line impedances. The ratio of the short-circuit to dynamic power is less than 7% for CMOS gates driving LC transmission lines where the line is matched or underdriven. Therefore, the total power consumption is expected to decrease as inductance effects becomes more significant is compared to an RC model of the interconnect.