Analysis of RC interconnections under ramp input
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Timing Models for MOS Circuits
Timing Models for MOS Circuits
Power dissipated by CMOS gates driving lossless transmission lines
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Power estimation in adiabatic circuits: a simple and accurate model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Approach to Energy Consumption Modeling in RC Ladder Circuits
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Modeling of Propagation Delay of a First Order Circuit with a Ramp Input
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Evaluation of energy consumption in RC ladder circuits driven by a ramp input
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mixed Full Adder topologies for high-performance low-power arithmetic circuits
Microelectronics Journal
Energy consumption in RC tree circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Closed form expressions are presented to accuratelydescribe the delay characteristics of RC tree networks.The Penfield-Rubinstein-Horowitz approach to estimating the stepfunction response of RC trees has been extendedto consider ramp inputs. This result improves timing accuracyby considering the shape of the input waveform driving each individualinterconnect tree while maintaining computational simplicityfor use in the automated timing analysis of complex VLSI circuits.