Ramp Input Response of RC Tree Networks
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
Power estimation in adiabatic circuits: a simple and accurate model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Power Digital CMOS Design
The Elmore delay as a bound for RC trees with generalized input signals
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Metrics and bounds for phase delay and signal attenuation in RC(L) clock trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy consumption in RC tree circuits with exponential inputs: an analytical model
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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In this communication, an approach to analytically estimate the energy consumption in RC ladder circuits is proposed. Effect of the input rise time on energy dissipated is modeled by assuming a ramp input. The approach is based on an exact analysis of energy dissipated by the network for asymptotic values of the input rise time. Successively, starting from the RC ladder circuits properties, a generalization is provided for arbitrary values of the input rise time. The approach followed leads to a closed-form expression of the energy dissipation. Moreover, this expression is formally equal to that of a first-order RC circuit, and is thus simple enough to be used for pencil-and-paper evaluation. The accuracy of the model has been tested by SPICE simulations. Results show that the energy predicted is in good agreement with simulated values.