Low-power digital systems based on adiabatic-switching principles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Ramp Input Response of RC Tree Networks
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
Design and Evaluation of Adiabatic Arithmetic Units
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
Low Power Digital CMOS Design
Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Metrics and bounds for phase delay and signal attenuation in RC(L) clock trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Approach to Energy Consumption Modeling in RC Ladder Circuits
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
On optimality of adiabatic switching in MOS energy-recovery circuit
Proceedings of the 2004 international symposium on Low power electronics and design
On optimality of adiabatic switching in MOS energy-recovery circuit
Proceedings of the 2004 international symposium on Low power electronics and design
Evaluation of energy consumption in RC ladder circuits driven by a ramp input
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimization of circuit trajectories: an auxiliary network approach
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Energy consumption in RC tree circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and modeling of energy consumption in RLC tree circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
A simple procedure to evaluate the energy consumption of adiabaticgate circuits is proposed and validated. The proposed strategy isbased on a linearization of the circuit and simplifying theanalytical result obtained on the equivalent network. The approachleads to simple relationships which can be used for apencil-and-paper evaluation or implemented on software. Theaccuracy of the results is validated by means of Spice simulationson an adiabatic full adder designed with a 0.8 μm technology.