A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
An Approach to Energy Consumption Modeling in RC Ladder Circuits
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Evaluation of energy consumption in RC ladder circuits driven by a ramp input
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Elmore delay as a bound for RC trees with generalized input signals
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this communication, RC tree networks are analyzed in terms of the energy dissipated during an input transition. A closed-form analytical model of the energy consumption is derived for arbitrary values of the input rise time by introducing a suitable first-order equivalent RC circuit, which avoids the explicit pole-zero evaluation. The proposed expression of the energy consumption has an evident meaning, thereby affording a deeper understanding of the network dissipation. Moreover, the energy model is sufficiently simple to be used in pencil-and-paper calculations. Extensive SPICE simulations confirm that the model has an adequate accuracy, as its error is typically within 5%.