Interconnect coupling noise in CMOS VLSI circuits

Noise estimation due to signal activity for capacitively coupled CMOS logic gates

GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI

Incremental physical design

ISPD '00 Proceedings of the 2000 international symposium on Physical design

An efficient analytical model of coupled on-chip RLC interconnects

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

A decoupling method for analysis of coupled RLC interconnects

Proceedings of the 12th ACM Great Lakes symposium on VLSI

The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections

Analog Integrated Circuits and Signal Processing

Repeater and current-sensing hybrid circuits for on-chip interconnects

Proceedings of the 13th ACM Great Lakes symposium on VLSI

Quality of EDA CAD Tools: Definitions, Metrics and Directions

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

A simplified transmission-line based crosstalk noise model for on-chip RLC wiring

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Reduced Delay Uncertainty in High Performance Clock Distribution Networks

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing

Proceedings of the 41st annual Design Automation Conference

Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory

IEEE Transactions on Computers

On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect

Noise separation in analog integrated circuits using independent component analysis technique

Integrated Computer-Aided Engineering

Data bus swizzling in TSV-based three-dimensional integrated circuits

Microelectronics Journal