Rectilinear Shortest Paths and Minimum Spanning Trees in the Presence of Rectilinear Obstacles
IEEE Transactions on Computers
Simulated annealing for VLSI design
Simulated annealing for VLSI design
Partitioning sparse matrices with eigenvectors of graphs
SIAM Journal on Matrix Analysis and Applications
Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
Optimization by simulated evolution with applications to standard cell placement
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A parallel bottom-up clustering algorithm with applications to circuit partitioning in VLSI design
DAC '93 Proceedings of the 30th international Design Automation Conference
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
An algorithm for incremental timing analysis
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A general framework for vertex orderings with applications to circuit clustering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
The quarter micron challenge: intergrating physical and logic design
Proceedings of the 1997 international symposium on Physical design
Proceedings of the 1997 international symposium on Physical design
The future of logic synthesis and physical design in deep-submicron process geometries
Proceedings of the 1997 international symposium on Physical design
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Multiway partitioning with pairwise movement
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fine grain incremental rescheduling via architectural retiming
Proceedings of the 11th international symposium on System synthesis
Dynamic Trees and Dynamic Point Location
SIAM Journal on Computing
Interconnect coupling noise in CMOS VLSI circuits
ISPD '99 Proceedings of the 1999 international symposium on Physical design
On the behavior of congestion minimization during placement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
VIA design rule consideration in multi-layer maze routing algorithms
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Interconnect estimation and planning for deep submicron designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
DUNE: a multi-layer gridless routing system with wire planning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Multi-center congestion estimation and minimization during placement
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Depth optimal incremental mapping for field programmable gate arrays
Proceedings of the 37th Annual Design Automation Conference
An implicit connection graph maze routing algorithm for ECO routing
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A sequential detailed router for huge grid graphs
Proceedings of the conference on Design, automation and test in Europe
Improved algorithms for hypergraph bipartitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
An Introduction to VLSI Physical Design
An Introduction to VLSI Physical Design
Bounded Incremental Computation
Bounded Incremental Computation
Incremental methods for FSM traversal
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
DAC '78 Proceedings of the 15th Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
A Graph-Theoretic Approach for Register File Based Synthesis
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Finding obstacle-avoiding shortest paths using implicit connection graphs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Incremental layout placement modification algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
GALLO: a genetic algorithm for floorplan area optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On crossing minimization problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level power modeling, estimation, and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Nostradamus: a floorplanner of uncertain designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decoupling capacitance allocation for power supply noise suppression
Proceedings of the 2001 international symposium on Physical design
Design technology productivity in the DSM era (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
On mismatches between incremental optimizers and instance perturbations in physical design tools
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
Proceedings of the 2003 international symposium on Physical design
Physical design methodologies for performance predictability and manufacturability
Proceedings of the 1st conference on Computing frontiers
Stable Multiway Circuit Partitioning for ECO
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
TAPHS: thermal-aware unified physical-level and high-level synthesis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Congestion driven incremental placement algorithm for standard cell layout
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Floorplan management: incremental placement for gate sizing and buffer insertion
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Adaptive chip-package thermal analysis for synthesis and design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Incremental component implementation selection: enabling ECO in compositional system synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Towards automated ECOs in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
A novel thermal optimization flow using incremental floorplanning for 3D ICs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
DeltaSyn: an efficient logic difference optimizer for ECO synthesis
Proceedings of the 2009 International Conference on Computer-Aided Design
An improved algorithm for sequence pair generation
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part I
Full Length Article: 3D thermal-aware floorplanner using a MILP approximation
Microprocessors & Microsystems
3D thermal-aware floorplanner using a MOEA approximation
Integration, the VLSI Journal
Intuitive ECO synthesis for high performance circuits
Proceedings of the Conference on Design, Automation and Test in Europe
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