Chip-level area routing

Authors:
Le-Chin Eugene Liu;Hsiao-Ping Tseng;Carl Sechen
Affiliations:
Department of Electrical Engineering, Box 352500, University of Washington, Seattle, WA;Department of Electrical Engineering, Box 352500, University of Washington, Seattle, WA;Department of Electrical Engineering, Box 352500, University of Washington, Seattle, WA
Venue:
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Year:
1998

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Abstract

We present a chip-level area router for modern VLSI technologies. The gridless area router can handle any number of layers, as well as rectilinear blockage areas on any layer. A two-stage divide-and-conquer strategy is applied so that the area router can handle very large chips. The first stage includes an area-minimization loop by using an efficient and accurate multi-layer global router. The global router minimizes the chip area while performing the global routing. According to the global routing results, switchboxes are generated for the whole chip area. Then the switchboxes are sent to the second stage for detailed routing, in which a tile-expansion based switchbox router is used. With multi-level rip-up and re-route techniques, the detailed router is shown to be able to complete many difficult switchboxes. The router was tested on the MCNC building block circuits. Our results show better chip areas than the best previously published results.