ISPD '98 Proceedings of the 1998 international symposium on Physical design
Timing and crosstalk driven area routing
DAC '98 Proceedings of the 35th annual Design Automation Conference
On the crossing distribution problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A novel technique for sea of gates global routing
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Pseudo pin assignment with crosstalk noise control
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Research directions for coevolution of rules and routers
Proceedings of the 2003 international symposium on Physical design
Proceedings of the 2008 international symposium on Physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Cross point assignment (CPA) for designs of general architecture is a layout problem that has not been well addressed so far. It is done before detailed routing and is to decide for each net the exact crossing locations on the boundaries of global routing cells (GRC's). To complete the CPA for a whole chip, an order of GRC boundaries needs to be decided, then a sequence of single boundary cross point assignment (SBCPA) tasks are performed. In this paper, we present a tool that performs iteratively the CPA process integrated with global rerouting. The CPA process applies a set of heuristic rules for boundary ordering and employs the well-known linear assignment algorithm to solve the SBCPA problem. For the algorithm we develop a novel and comprehensive cost function that can, in addition to minimizing wire length and via count, reduce the effects of horizontal/vertical constraints, and consider globally the wire topologies in a GRC row or column. Moreover, by performing global rerouting based on accurate congestion status after each CPA iteration, the tool can produce, with a well-improved global wire routing, the final CPA result of each GRC. The result can usually be directly input to detailed routing with much higher completion rate and thus can relieve the efforts of post-routing clean up. This tool has been tested on several gate-array and sea-of-gates chips. In particular, the benchmark chips, Primary1 and Primary2 have been successfully routed with about 17% track usage improvement