Performance-driven interconnect design based on distributed RC delay model
DAC '93 Proceedings of the 30th international Design Automation Conference
Rectilinear Steiner trees with minimum Elmore delay
DAC '94 Proceedings of the 31st annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Performance driven global routing for standard cell design
Proceedings of the 1997 international symposium on Physical design
DAC '83 Proceedings of the 20th Design Automation Conference
Cross point assignment with global rerouting for general-architecture designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present a novel global routing and cross-point assignment methodology for sea-of-gates (SOG) designs. Using the proposed congestion driven spanning trees (CDST), and continuously analyzing the congestion at all steps, nets are incrementally globally routed in one of the six well thought of heuristic steps of our methodology. This eliminates the need for rip-up and re-route and enables our approach to achieve good completion rates. We tested our flow on a number of testcases from the industry. The net lengths produced by our flow were compared to the theoretical lower-bound (steiner tree) and were found to be at most 4% worse. We compared the results of creating the net segments by the classical MST verses the CDST and observed an 80% improvement in the number of incomplete nets. Completing the detailed routing using a commercially available detailed router validated the results of the proposed global routing and cross-point assignment.