New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing

Optimal wiresizing for interconnects with multiple sources

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Buffered Steiner tree construction with wire sizing for interconnect layout optimization

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Timing optimization for multi-source nets: characterization and optimal repeater insertion

DAC '97 Proceedings of the 34th annual Design Automation Conference

Interconnect layout optimization under higher-order RLC model

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Performance driven global routing for standard cell design

Proceedings of the 1997 international symposium on Physical design

Routing tree topology construction to meet interconnect timing constraints

ISPD '98 Proceedings of the 1998 international symposium on Physical design

Table-lookup methods for improved performance-driven routing

DAC '98 Proceedings of the 35th annual Design Automation Conference

A simultaneous routing tree construction and fanout optimization algorithm

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model

ISPD '99 Proceedings of the 1999 international symposium on Physical design

Timing driven maze routing

ISPD '99 Proceedings of the 1999 international symposium on Physical design

FAR-DS: full-plane AWE routing with driver sizing

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

MERLIN: semi-order-independent hierarchical buffered routing tree generation using local neighborhood search

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

A novel technique for sea of gates global routing

GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI

Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Buffered Steiner trees for difficult instances

Proceedings of the 2001 international symposium on Physical design

Buffer insertion with adaptive blockage avoidance

Proceedings of the 2002 international symposium on Physical design

Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages

Proceedings of the 2002 international symposium on Physical design

S-Tree: a technique for buffered routing tree synthesis

Proceedings of the 39th annual Design Automation Conference

A timing-constrained algorithm for simultaneous global routing of multiple nets

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

A novel framework for multilevel routing considering routability and performance

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Non-tree routing for reliability and yield improvement

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Concurrent flip-flop and repeater insertion for high performance integrated circuits

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

An O(nlogn) time algorithm for optimal buffer insertion

Proceedings of the 40th annual Design Automation Conference

An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

An efficient hierarchical timing-driven Steiner tree algorithm for global routing

Integration, the VLSI Journal

Full-Chip Multilevel Routing for Power and Signal Integrity

Proceedings of the conference on Design, automation and test in Europe - Volume 2

A fast algorithm for identifying good buffer insertion candidate locations

Proceedings of the 2004 international symposium on Physical design

Fast and flexible buffer trees that navigate the physical layout environment

Proceedings of the 41st annual Design Automation Conference

An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Moment-driven coupling-aware routing methodology

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI

Efficient generation of short and fast repeater tree topologies

Proceedings of the 2006 international symposium on Physical design

Efficient algorithms for buffer insertion in general circuits based on network flow

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Steiner network construction for timing critical nets

Proceedings of the 43rd annual Design Automation Conference

Design and verification of high-speed VLSI physical design

Journal of Computer Science and Technology

Maze routing steiner trees with effective critical sink optimization

Proceedings of the 2007 international symposium on Physical design

Full-chip multilevel routing for power and signal integrity

Integration, the VLSI Journal

Layout-aware gate duplication and buffer insertion

Proceedings of the conference on Design, automation and test in Europe

Utilizing redundancy for timing critical interconnect

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Maze routing Steiner trees with delay versus wire length tradeoff

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Timing-driven, over-the-block rectilinear steiner tree construction with pre-buffering and slew constraints

Proceedings of the 2014 on International symposium on physical design