Performance-driven interconnect design based on distributed RC delay model
DAC '93 Proceedings of the 30th international Design Automation Conference
Rectilinear Steiner trees with minimum Elmore delay
DAC '94 Proceedings of the 31st annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Buffered Steiner trees for difficult instances
Proceedings of the 2001 international symposium on Physical design
Closed form expressions for extending step delay and slew metrics to ramp inputs
Proceedings of the 2003 international symposium on Physical design
Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Placement driven synthesis case studies on two sets of two chips: hierarchical and flat
Proceedings of the 2004 international symposium on Physical design
A Novel Performance-Driven Topology Design Algorithm
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Obstacle-avoiding rectilinear Steiner tree construction
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree
Proceedings of the 2009 International Conference on Computer-Aided Design
FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction
Proceedings of the 19th international symposium on Physical design
An exact algorithm for the construction of rectilinear Steiner minimum trees among complex obstacles
Proceedings of the 48th Design Automation Conference
A new heuristic for rectilinear Steiner trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast Algorithms for Slew-Constrained Minimum Cost Buffering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Closing the gap: near-optimal Steiner trees in polynomial time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An edge-based heuristic for Steiner routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the International Conference on Computer-Aided Design
Construction of rectilinear Steiner minimum trees with slew constraints over obstacles
Proceedings of the International Conference on Computer-Aided Design
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In this paper, we study a fundamental and crucial problem of building timing-driven over-the-block rectilinear Steiner tree (TOB-RST) with pre-buffering and slew constraints. We pre-characterize the tree topology and buffer distribution to provide accurate timing information for our final RST construction. In most previous work, the routing resources over the IP blocks were simply treated as routing blockages. Our TOB-RST could reclaim the ``wasted'' over-the-block routing resources while meeting user-specified timing (slack and slew) constraints. Before fixing topology, a topology-tuning is performed based on location of buffers to improve timing without increasing buffering cost. Experiments demonstrate that TOB-RST can significantly improve the worst negative slack (WNS) with even less buffering and wirelength compared with other slack-driven obstacle-avoiding rectilinear Steiner tree (SD-OARST) algorithms.