Steiner network construction for timing critical nets
Proceedings of the 43rd annual Design Automation Conference
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Revisiting fidelity: a case of elmore-based Y-routing trees
Proceedings of the 2008 international workshop on System level interconnect prediction
Utilizing redundancy for timing critical interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Combinatorial algorithms for fast clock mesh optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2014 on International symposium on physical design
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The "chicken-egg" dilemma between VLSI interconnecttiming optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as Hanan grafting and non-Hanan sliding, andreveal generally negligible contribution of non-Hanan sliding. We propose a greedy iterative interconnect timing optimization algorithm called Q-Tree. Our experimental resultsshow that Q-Tree starting with Steiner minimumtree topologies achieves better timing performance than C-Tree [1],PER-Steiner [5] and BA-Tree [14] algorithms. Also, executing Q-Tree starting with BA-Tree or P-Tree [13] topologies can achieve better timing performance, especially, withshorter wires and fewer buffers. In general, Q-Tree canbe applied to any interconnect tree for further timing performance improvement, with practical instance sizes andeasily-extended functionality -e.g., with buffer station androuting obstacle avoidance consideration.